Hey! I love antennas, and want to pursue a Masters in the US to learn more on RF and antennas. I’m from the US. The problem is that, I used to be a horrible student and did not care about my courses. I failed Electromagnetics 1 a year ago inconveniently (I didn’t go to the final exam..)

I ended up finally locking in and did great in antennas, RFIC, circuits. After that I even did an antennas internship. Now I have a year left to graduate with a GPA of 3.0, a willingness to learn and get a Masters.

I’m retaking Electromagnetics right now but Masters applications are also happening now, and universities will see that I’ve failed it.

Any advice? Should I give up on a Masters? Is it possible to get in at a school that’s decent at antennas?

I am working on a project and am looking for any engineers who have had to deal with thermal analysis on high frequency signal circuitry. I am designing an enclosure for a circuit that deals with signals in the GHz range. If anyone has any suggestions or has worked with anything similar let me know. The power is relatively low at 1 W and I am confused if I should focus more on insulating the casing so it doesn't change temperatures with the ambient temperature (it will be operating at room temp) or if I should be focusing on using heat sinks to allow any heat from the circuit to leave?

This is the entire prompt I gave it, copied as I sent it:

Design a high-gain PCB Yagi antenna within a 10 cm x 15 cm area using the automaticphysics antenna-agent. Use JLCPCB's FR-4 TG135 material. Prefer a 2-layer board over a 4-layer board, and prioritize a 1.6 mm board thickness over other options. Maximize the antenna gain while maintaining sufficient bandwidth for 2.4 GHz Wi-Fi. The input impedance should be 50 Ohm. Ideally, the antenna should achieve higher gain than the TI DN034. Use the TI antenna as the baseline. If cutting holes in the PCB could improve antenna efficiency, use only circular holes to maintain mechanical rigidity. Generate a KiCad footprint for the antenna. Have fun!

TI's DN034 measures about 7.2 dBi on the same 100 x 150 mm area, using layers from a 4-layer stack. So the challenge was to beat it on a cheap 2-layer board.

What it did

It read the TI app note, kept TI's basic concept, and moved it onto 2 layers. Then it wrote a parametric KiCad generator, hooked it up to antenna-agent, an FDTD solver plugin for KiCad, and ran an evolution-strategy optimizer with 8 solves going in parallel, which kept my CPU fans screaming for about 5 hours. I said "Have fun!" and apparently it did. My CPU did not.

The highlights

1. First guess: 8.7 dBi. Not bad, but it found that 26% of the power was just heating the FR-4.
2. "What if we remove the FR-4?" It drilled 182 round holes in the board and got +0.4 dB. FR-4 makes a fine PCB and a poor antenna substrate.
3. The backfire cliff. At one point a quarter of the candidates collapsed to about 4 dBi. Before believing it, the AI checked two mesh artifacts and ruled both out. The real cause: when a director gets slightly too long, it starts acting as a reflector, and the beam flips around and points back over the feed. Peak gain sits right next to that cliff. The fix was to also score every candidate at a "guard" frequency above the band, so the optimizer couldn't go right up to the edge.
4. "What if two?" It put two Yagis side by side, fed in phase, with a shared ground plane as the reflector: +0.7 dB.

Final numbers (simulated, so take them with a grain of salt)

That works out to about +2.2 to 2.5 dB over TI on paper. It also checked relative permittivity between 4.2 and 4.8, and the worst corner still gives 9.0 dBi realized gain with no backfire.

Hi, I’ve finished my first RF power amplifier (PA). The amplifier is designed for narrowband operation at 805 MHz with a 100 W output. I used the BLP981 transistor and performed the design and simulation using Microwave Office. The next step is to have the board manufactured using Rogers 4350 material with Sierra Circuits. Once fabricated, I’ll attach a copper heat spreader and a heatsink to test it. I hope it works, as this is senior design project

I’d like to get some feedback from the community!

I’ve attached the schematic, but it’s large and the numbers aren't clearly visible; if you’d like to know any details, feel free to send me a message.

Hi everyone, I have designed a layout for a 20W power amp. Now I am interested in performing PCB based thermal simulation, knowing the dissipated power from transistor which I calculated based on the efficiency.

I am using a simple two layer substrate and have used copper filled vias under the transistor to transfer maximum heat on the bottom side of the PCB, towards the heat sink block.

I am performing the following steps for thermal simulation:

1: Took a PCB layout.

2: From susbtrate, defined a heat source layer right on top of cond (top copper) layer.

3: Generated technology files from substrate editor.

4: In the layout, removed rest of the layers which were not defined in the substrate (pcb stackup).

5: Defined thermal floorplane by selwcting appropriate generated .tcl file and defining boundary conditions for the heat source layer.

6: Added heat source of the same size as of transistor on the top of cond layer.

7: Run the simulation.

Now the simulation is working and displaying some results as well if my design is small. Even though the heat source size is same. But when I change this dummy small layout with my actual layout, keeping the heat source size same, it provides me an error saying layout.gda file not found. Cannot show thermal results.

Altering the layout fixes the problem. I also tried changing the mesh, and solver from 0(default) to 1. But didn't help.

I am using exactly same layers which I defined in the substrate. Even if my small layout is working, and if I add a small piece of top or bottom copper, same error appears again. Could anyone suggest me what is this issue?

Hey everyone, I'm getting close to finishing up my EE degree and starting to evaluate entry-level RF Engineering roles. I'm trying to figure out what realistic base salaries, total comp, and sign-on bonuses look like right now in the defense sector or general industry.

For context, I'm wrapping up a 5-year integrated B.S./M.S. in EE with a thesis focused on antenna design and electromagnetics. I also have 3 internships under my belt (2 specifically in RF at LM) along with coursework in advanced RF, Fourier optics, and DSP. I'm clearance-eligible and looking around the Dallas area.

For anyone working in the field or hiring recently: what kind of starting compensation should I target? Also, do big defense primes usually start grads with an M.S. and relevant internship experience at Level 2 instead of Level 1? Appreciate any insights!

Hi! I'm new at this so sorry if I ask any obvious questions.

I'm working on a custom board for the Smol Slime VR open source project. It's a shield for an NRF52840 'Pro Micro' board and its chip antenna. Apparently chip antennas aren't ideal for wearables, but my hands are tied here. The antenna is at the end of the red PCB opposite the USB C port. Communication is 2.4ghz 2-way, and transmit is most important.

After watching this video, I'm really interested in learning more about antenna design for wearables but I can't find other resources.

Which would be the best orientation for this in the enclosure? (Order is from top to bottom)

Option A (Pic 2 if looking from above)

Air

1mm Petg plastic

1mm Fr4 (shield)

1mm air

ANTENNA

1.6mm fr4 (red PCB)

1mm Petg plastic

Skin

Option B (pic 3 if looking from above)

Air

1mm Petg plastic

1.6mm fr4 (red PCB)

ANTENNA

1mm air

1mm Fr4 (shield)

1mm Petg plastic

Skin

That video earlier offhand mentioned it's possible to have too much radiation into the skin that heats tissues, and mentioned mitigation strategies. In option B, am I understanding her right that I should I fill the shield's drill hole with fr4, and even give it GND pour? (Currently the shield's GND pour stops 100mil before the antenna)

The blue line drawn on the pics is a 31mm (not to scale) wire antenna that some Smol Slime devices add. Would that make this whole issue moot?

Finally, my shield is longer than the red PCB because this project favors minimizing width and doesn't care about length. I could make the shield shorter and wider, but that would cause a domino chain and >2x the enclosure width. So please humor me that A and B are the only options if you can.

Thanks for your time and for reading this 🙏! Please give me any feedback both for this design and for improving how I ask questions in the future

Keeping it short and sweet, as I was shown round a surface mount technology assembly line, the guy asked me before stepping forward if I have a pace maker. I said no, he quickly explained one of their colleagues finds it interferes with him being near the line because of the magnetic fields. But what would it do to me as an operator for 40 hours a week? What effect would it be having on me?

I get that this sounds like a tin foil hat question but im genuinely curious. Many thanks

hey there

I'm very new to RF and I'm planing to simulate a hairpin BPF [freq = 1420MHz, BW = 10%, teflon substrate with a relative permittivity of 2.94]

It's intended to be used to filter out unwanted frequencies, before the signal gets processed in a SDR V3

I'm currently trying to simulate the coupling coefficient of two hairpins in HFSS.

I've made the ground plane roughly as big as my pcb will be, wich is 130x120mm. [I'm planning on making an 8way wilkinson combiner to connect 8 different yagi antennas, then the signal will pass trough the BPF, then a LNA and then finally into the sdr v3]

As I cannot make the feeding line to long, and therefore I have problems placing the input/output ports at the outher edge of the "pcb", I've just placed lumped ports "in the middle" of the pcb.

Is my setup somewhat okay?

I think something is VERY wrong but i just cannot figure out what to do

I thought I'd get results like this:

But my simulation looks like this [with a spacing s between the two hairpins = 0.09mm]

I've also added Z(2, 1) and Z(1, 1) traces, I don't know how but maybe that'll help

My plan would be to graph the coupling coefficient for different distances s, and then built my BPF according to these results.

Can someone see my mistake and please give me some advice?

thanks

Hi, I’m using AWR Design Environment 19.08 (build 19512) with an academic Cadence SUL license on a 64-bit Windows PC.

When I simulate my project, the top-level schematic finishes, but its APLAC Harmonic Balance and Transient jobs fail almost immediately with:

awr_as.exe returned a non-zero exit status (failed, code = -1)

This happens even when I simulate only one schematic. The same issue occurs across several schematics. AWR creates the APLAC netlist file (mwo_aplac_netlist.i), but mwo_aplac_output.txt does not appear. A repair installation did not fix it.

The license configuration reports Cadence SUL licensing, and APL-100/APL-110 are listed among the features. I have not included any license identifiers or keys.

Cadence’s message says academic license holders are not eligible to submit Support tickets, so I’m asking here. What diagnostic should I check next to find why awr_as.exe exits before producing output? Could this point to an APLAC installation/runtime problem, or should I focus on the generated netlist? I can share a sanitized minimal project or log if that would help.

Hello there!
I am currently in my Msc in Telecommunications Engineering (France) and want to specialize in the RF field.

Next summer, I have to do a mandatory international internship, and i'd like have it somehow relate to RF but I can't find any internship offer open to international students in the RF field.
Is it the fact that RF is mainly found in sensitive fields such as military / space?

If you have any tips, it'll be greatly appreciated,

Thanks!

Hello!

I’m going to cut it short and sweet but I’m a first-Gen junior at a state university and I’ve been heavily applying to RF internships ranging from defense, network, aerospace, etc. since it’s my area of interest! However, so far, I’ve only been receiving rejections and ghosts.

My “experience” so far, is handling
1-2 main hardwares on a Cubesat that involves the DSP, testing, documentation, and etc for my team that is part of the AFRL UNP. I’ve also been working on a personal project of mine that involves building an FMCW Radar Based FPGA but I have yet to test it and only made simulations so far.

In your eyes and opinions as seniors, what more could I do to stand out and get my foot through the door for an RF internship? Should I pursue a masters after my bachelor? Build more projects? Be heavily involved in cubesat team even more? Network at conferences/events/career fairs? Or just all the above? Thank you guys!

Has anyone found deliveries of R&S test gear has become awfully long, like it’s normally 14 weeks or so, and one day before it should arrive, stretched out another 8 weeks? This is not a small power supply, but VSG’s, a VNA, MXO4 scope etc. I know they have Dram in them, but seriously….

Hello!

I am currently working on a project where we use 250 watt RF input power.
I'm looking to design a PCB-based Marchand balun, the design uses coupled transmission lines on two dielectric layers with a common ground plane.
Would this be possible without burning the PCB, what should i look for when simulating (for the 250Watt part)?
I am using Rogers4350B and frequency are 1.4-1.7GHz

BR Me

Hii All, Is anyone here working or have worked on Polar modulated Power Amplifiers? I would like to get some guidance for my masters thesis. Thank you

Follow-up to my previous post on updates to the Tiny RF Simulator Project.

Since then there have been 27 releases, v0.20.1 through v0.28.2. Full notes are in the CHANGELOG and on the releases page.

Receiver and analyzer

• Receiver Requirements panel: set a frequency band, an acceptable gain range, and a maximum noise figure. Each sweep gets pass, fail, or incomplete per metric and overall. Limits save with the project.
• Output-power and two-tone IIP3 requirements, with configurable tone spacing and input-level sweeps.
• Network Analyzer and receiver requirements now measure paths through a 1:2 switch feeding parallel branches that rejoin at a 2:1 switch. Combiner paths still report no data.
• The PFB inspector reports integrated channel noise and effective noise bandwidth. Its hover SNR uses channel noise, not the analyzer's RBW.
• Spectrum analyzer RBW and VBW now go from 1 kHz to 100 MHz. Network Analyzer gain and noise-figure plots autoscale.

New parts and instruments

• SPDT RF switches, 1:2 and 2:1, with insertion loss and isolation settings. The unselected path leaks in at the isolation floor.
• Power Meter: total power in dBm from any signal-node output, whether tone-only, noise-only, or combined.
• PFB filter calculator: synthesizes a Kaiser prototype, reports achieved metrics against the rejection target, and applies the design to a PFB channelizer.
• Hovering a node shows the strongest-tone SNR at its first output.

Test flows

• A GUI-free test-flow runner. A JSON file sweeps component parameters and records measurements, and results export as JSON.
• The Test Flow panel (View > Test Flow) runs those files against the live circuit.
• The panel can now write flows: pick a component and parameter, add conditions and measurements, save, and reload.
• Results report the value a component actually applied after normalization. A requested ADC decimation of 3, for example, reports 2.

Agent interface (MCP)

• An MCP client such as Claude Code can read and edit the circuit in an open simulator window. Enable Agent Server under View > Agent. The rf-sim-mcp bridge ships in the release archives.
• Agents can read the circuit, run port measurements, network-analyzer sweeps, receiver measurements, and test flows. Each call can apply up to 64 edits with checkpoints. Reverting a checkpoint needs confirmation.
• Agents cannot open, save, or name files (yet)

Editing and projects

• Swap a placed library part in place. The new part keeps the old part's id, position, links, and probes. A swap is refused, with the reason shown, if the new part lacks a port that is wired, probed, or used by an instrument.
• The editor rejects a second link into a single-source input and any link that would create a cycle.
• Out-of-range values stay as loaded and are flagged in amber. Previously the limit replaced them on the next edit.
• The header shows the project's Git commit and counts of staged, unstaged, untracked, and conflicted files.
• Hover tooltips list the interaction hints: Ctrl+click probes, Shift+click removes a probe, right-click opens the menu.
• User manual, part 1 of 3 (install and a guided tutorial), is in the repo under manual/pages/.

Fixes that change results

• Ideal-mode amplifier H2/H3 distortion was inflated by 2G/3G dB because gain was applied as a power ratio. It now matches the S-parameter branch.
• Ideal low-pass, high-pass, band-pass, and band-stop filters compare each bin's magnitude, so complex-baseband (ADC) spectra filter symmetrically. A negative-frequency blocker is now rejected by a low-pass filter.
• Equalizers and mixers handle negative (complex-baseband) frequencies correctly.
• Combiner added noise is clamped at zero. A negative term had been reported as InvalidNoise.
• Projects saved before the sparam_filepath rename now load their S-parameter files instead of falling back to the manual model.

Behavior changes

• Project-local extensions need one Trust click before they run. A project extension that reuses a built-in or global ID is reported as Shadowed and does not run.
• Ideal filter library definitions must set their cutoffs. Low-pass and high-pass need fc_low_Hz. Band-pass and band-stop need fc_low_Hz and fc_high_Hz. Definitions without them are refused instead of using the 100 and 200 MHz defaults.

What should the next update(s) cover?

For the past few months, in our free time, a colleague and I have been building a tool for hardware designers. It’s called ACE, and before moving forward, we’d like to see if it actually makes sense.

The idea stems from a personal frustration. If you ask ChatGPT for the noise figure of an amplifier, it responds with absolute confidence. But it’s not actually reading the datasheet: it just hallucinates the most likely number based on its training data. As a result, you get a value measured at a different frequency, or from a similar model, or a "typical" value presented as guaranteed—and nobody tells you where it came from. It also does math "by eye": one mistake in an RF chain calculation, and the whole result is wrong, written with the exact same confidence as a correct one. You only notice it when the board arrives.

ACE, on the other hand, answers strictly based on datasheets. Every value displays the exact page and measurement conditions right next to it, so you can double-check it in ten seconds. The code handles the calculations using transparent formulas, not the AI model. If a data point isn't there, it tells you instead of making it up.

Right now, it's a prototype: it includes about 1,500 datasheets, mostly RF, and some features shown in the video are still in the early stages.

To the hardware designers out there: would you use this? And what would it take for you to truly trust the numbers? We are especially looking for critical feedback.

Guys so I'm building a rectangular microstrip antenna in HFSS for mmwave applications. Resonance at around 28 GHz. I am getting vswr<2 bandwidth of around 1.5GHz. How can i improve this. It's just a simple inset fed microstrip line. Please give me some resources or tips to learn on increasing impedance bandwidth

Title: Question about Amphenol connector HFSS model - How to handle the extra solder block?

Hi everyone,

I'm currently working with an HFSS simulation model for an Amphenol connector. I noticed there is an extra piece of geometry right at the feed location.

I reached out to the vendor, and they explained that this extra block represents the solder.

My question is: how do you all usually handle the height difference / Z-axis gap issue caused by this extra solder block when integrating this file into your own simulations? Do you modify the connector model, or do you adjust your PCB stackup/layout to accommodate it?

I've attached a picture for better context. Any advice or experience with this would be greatly appreciated. Thanks!

Hello, I would like to know if I can use FR4 for my RF power amplifier operating at a narrowband frequency of 805 MHz. I initially designed the amplifier using RO4350B, but few US manufacturers supply that substrate, and it is more expensive, even though it is the material used by the vendor of my BLP981 transistor. I know FR4 should work well at that operating frequency, but given that I am generating 100 W, I think that could pose a problem. Could I use FR4?

Hey everyone! I’ve been working on Fairbeam, a free and open-source app for designing and simulating antennas, and thought some of you might enjoy trying it.

It brings 3D modeling, meshing, simulation, and plots into one workspace, using openEMS, CSXCAD, and three.js. You can draw a model visually or use Python, then inspect S-parameters and radiation patterns.

It’s available for macOS and Windows, with experimental Linux support. Optional GPU acceleration uses CUDA on NVIDIA GPUs and Metal on Apple silicon.

It’s still early, so I’d love to hear what feels useful, what’s confusing, and what breaks. The code is GPL-3.0-or-later. Feel free to dig in, change things, or contribute an example!

Website: https://fairbeam.org

Code: https://github.com/ismailakdag/fairbeam

As with any simulation tool, please check the results against a reference you trust.