Sorry if this is a dumb question.

Sono lo sviluppatore di SILICON ( [), un simulatore di circuiti digitali gratuito e open-source scritto in C++ utilizzando Qt6.

Diventerà la mia tesi di laurea (studio Ingegneria Informatica a Genova, Italia) e lo stiamo sperimentando nel corso di progettazione digitale presso la mia università (UniGe).

SILICON si propone di fornire un ambiente moderno per la progettazione e la simulazione di circuiti digitali, principalmente a scopo didattico (come LogiSim), integrando gradualmente funzionalità EDA più avanzate.

Alcune delle sue funzionalità attuali includono:

1. Editor grafico di circuiti con porte logiche, componenti aritmetici, flip-flop, registri, ROM e altro (simile a LogiSim).

2. Simulazione digitale basata su eventi con bus multi-bit e logica a quattro stati (con circuiti ciclici simulati tramite componenti fortemente connessi e analisi di convergenza).

3. Visualizzazione in tempo reale delle forme d'onda e modifica delle forme d'onda di input con supporto di prima classe per FST.

4. Importazione/esportazione Verilog tramite integrazione Yosys. Il codice Verilog viene tradotto in un circuito grafico come avviene negli EDA.

5. Sottocircuiti riutilizzabili e progetti multi-documento.

6. Editor di codice e binari integrati, insieme a strumenti ISA sperimentali (riconoscimento e visualizzazione del formato delle istruzioni).

7. Compilazione tramite browser con WASM.

Apprezzerei in particolare un feedback sull'interfaccia utente, sul comportamento della simulazione, sulle funzionalità mancanti e su eventuali bug riscontrati.

Se desideri contribuire come sviluppatore, inviami un messaggio privato. Ho bisogno soprattutto di aiuto con il supporto per MacOS e il packaging per Windows.

P.S. So che il sito web è stato realizzato con l'IA, ma avevo bisogno di qualcosa di utile in fretta e non sono molto bravo con lo sviluppo web frontend. Tuttavia, ho definito completamente l'aspetto grafico del software e del sito web perché volevo un look molto particolare ;)

This is the first CPU that I have built of this caliber. Specs are: 3 general purpose registers, 256 bytes of ram, 256 bytes of program memory, 8 bit program counter, 8 bit memory pointer, 5 bit OP code with 23 instructions, and overflow, carry and zero flags. This took me roughly 50 hours in total over the course of a month to put together. Overall I am very proud of myself. What are some simple programs that I should write for it?

I've been trying to replicate the CD4013B flip-flop in Logisim Evoluition 5 according to 1975 RCA documentation (CD4008A worked out quite well), but the transmission gates are giving me a headache. Because transmission gates (even built-in) are alternating, I can't pass the input to the salve section, it's always either error or undefined. If I deviate and flip the polarity of either of the TGs, the input (wrong one) passes through when the clock is on, but the NANDs display red when the clock is off. I wonder if it's Logisim's limit or am I missing something?

hola, tengo que hacer un shifter de 8 bits igual a la imagen adjunta pero tengo que sacar la operación division (nDIV) y remplazarla por NOT OPERATION, osea , el numero que pongo en la entrada es el mismo en la salida, mi profesor me dijo que tengo que cambiar solamente el cableado, las AND de los extremos podria sacarlo o dejarlo como esta , eso lo tengo que pensar me menciono, me ayudan ?? solamente cambiar el cableado, no agregar nada si no es muy necesario . gracias :c

When I go forward half a clock cycle it immediately seizes. Any help would be appreciated, thanks in advanced.

I'm trying to map out a circuit diagram for a railway crossing, and I noticed that "improvised" SR flip-flops (made of two cross-connected NOR gates) behave weirdly compared to "proper" ones. At the start of a simulation, they're both giving an error output, which the diagram treats as a high until I've clicked all four ON and OFF buttons, after which everything starts functioning properly. Is it just a Logisim quirk or am I actually doing something wrong here?

I need help buildidng this for my project and i dont know how to do it. can someone guide me please :)

I am looking for a proper memory mod for logisim-evolution 4.0.0, with either a memory component or something else, that would allow me to store data between sessions because the "non-volatile" option on the program's built-in RAM component just refuses to work and it's getting annoying that I always have to rewrite programs and crap of such, and I would be very thankful if someone would recommend me a mod or add-on with a component or feature that would help. thanks in advance: :)

https://github.com/MODERN-DAY-COMPUTING-SYSTEM/PROJECT
Would recommend you to do this too in your summer vacation.

https://mrprodoja.itch.io/redstone-logic-sim

Can someone help me with a digital electronics project? I need a toy that features an electrical circuit built using ICs and logic gates, as I have to present a prototype. I’m really struggling to assemble it on platforms like Tinkercad and Logisim; I’ve tried working on various toy designs, but the logic keeps failing. If anyone could recommend a design and has a completed project to share, I would be very grateful.

save to a .circ file and enjoy the hot mess

https://pastebin.com/CfyiCS2j

https://www.youtube.com/watch?v=PW9oS5Yi38o

What exactly is wrong with the input A? I am new to logisim and it would be really helpful ig some one guides me out of this. i was building 8 bit ALU (yeah iam very VERY beginner) and A is a 8 bit pin. But when i connected it to the previously made Full adder circuit, it just does not take it in or what ever this is called.

Try it here https://8gwifi.org/electronics/logic-simulator.jsp

I built a D flip-flop from scratch in Logisim.

The circuit appears to work correctly during manual simulation. After a few clock ticks, the outputs behave exactly as expected and the latch stores values properly.

However, I have two issues:

1. Before the simulation starts, the right part of the latch is red. But after manually ticking the clock a few times, the circuit works normally.
2. When I try to start the Timing Diagram, Logisim crashes. I also get the message "Oscillation apparent" at the bottom of the window.

My question is: could this be caused by the latch starting in an undefined state due to the feedback loop, even though the circuit itself is logically correct? Has anyone seen Timing Diagram crash because of an uninitialized latch or RS feedback structure?

The circuit works after initialization, so I'm trying to understand whether this is a bug/limitation of Logisim or an actual design issue on my side.

im building a 32 bit risc architecture cpu and i wanted some opinions and advice on it

so far I have built the ALU and the register file. ALU consists of all operations that risc has, Register file consists of 32 registers of 32 bits each and i had another 32 bit register to temporarily store output that the ALU generates.

I initially wanted to do 64 bit arch but the version of logisim I had was only restricted to 32 bit. I am most probably going to build the control unit next but wanted advice on this so far and if I've made any mistakes.

Also one small change that I have made in this is input can be written to registers in 2 ways, either all bits are written or only selected bits are written, just an enable logic is added to switch between the modes i sorta took inspo from other archs for that.

Lemme know what u guys think I have attached the necessary files ss as well

ps ik premade components already exist of some of the parts I have built but that was just to get a better in-depth knowledge about the whole thing

this is me showing basic operations of the alu and register storing of the alu ouput