Back in 2022/2023 I was particularly interested in open source ISA for FPGA soft core processors so I started working on my own called OASIS. Its an open source ISA that I designed to be a lot easier to work with than RISC-V. Not that RISC-V is bad by any mean, it wasn’t nearly as straightforward as I hoped it would be to implement one. And I know, implementing a custom ISA isn’t exactly the easy route to understanding soft cores and processors at all. lol…

Anyway, I put it down in 2023 because I got bored and was doing other hardware things and work was pretty busy. I picked it back up this year to get it formalized documentation and implementation wise. I did use Codex to help fix some of my blatant RTL mistakes in my implementation core that I call DungV. that name is a bit of a joke for me because I wasn’t sure what I was doing 😅

Anyway, here’s the high level details on DungV with is running on my own RPGA Feather.

* 16b architecture with 32b wide instructions

* ALU that does a fair number of operations except for multiplication and division.

* Memory Mapped IO and peripheral instructions.

* 4 classes of instructions (reserved, ALU, register, memory)

* full intermediate support since the instructions are sufficiently wide.

* assembler and basic GCC14 compiler and ABI definitions.

Let me know what you think!

Anyway, here is the repo hosted on GitHub: https://github.com/skerr92/DungV

Hello everyone,

Currently, I am pursuing my studies in Electronics and Communication Engineering and I am in my 7th semester. I am trying to improve my profile for internships and entry-level positions in the semiconductor industry.

I would like an honest critique of my resume, especially from people working in chip design, verification or other hardware roles.

My main interest are RTL design, digital VLSI, ASIC front-end design, design verification and digital hardware based on FPGA.

I’d love feedback on these questions in particular:

1. Does my resume demonstrate enough technical depth for an internship or entry-level role, or do my projects look too academic?
2. Which sections of my resume would cause you to toss it out immediately?
3. What projects or skills should I work on to be a better candidate?
4. Where should I look for small semiconductor startups or early-stage chip design companies that are offering internships or entry-level positions?
5. Are there any specific platforms, company directories, startup communities or job boards to follow for RTL, ASIC, FPGA and digital design verification roles?

Seeking internships or appropriate full-time opportunities. I'm especially interested in working at smaller companies where I can get hands-on design and verification experience.

Be honest, even if the feedback is brutal. I’d rather know my weaknesses now than continue applying with a noncompetitive resume.

Thanks!

I have commonly using Digilent's Arty A7-35T. But I cannot execute code on board. Everytime when i press auto connect or find device on Vivado, my pc crashes Instantly with page fault in nonpage area and kernel security check failure error messages. I've been used Zedboard but my pc never crashed down

They make relatively inexpensive FPGAs, but I find their IDE/EDA confusing to use.

I wonder if anyone uses them a lot and has found it to be a good brand.

We're based in San Francisco and looking to rent AMD Alveo V80 cards. Does anyone know of rental providers or have cards they'd be willing to rent out?

Would appreciate any leads or contacts. Thanks!

October 21, 2026 at 2pm ET (NYC time)

REGISTER: https://bltinc.com/xilinx-training/blt-webinar-series/debugging-embedded-applications-using-vitis-ide-system-debugger/

Can't attend live? Register to get the recording!

BLT, an AMD Platinum Embedded Design Services Partner and Authorized Training Provider, presents this webinar.

When embedded applications misbehave, engineers need clear visibility into execution flow, stack usage, and memory behavior to find the root cause quickly. This webinar shows how to use the AMD Vitis Unified IDE system debugger to step through code, set breakpoints, and monitor or modify variables and memory in real time. Using a recursive Towers of Hanoi example, we will explore the call stack and execution control techniques that help diagnose hard-to-find bugs, validate algorithms, and reduce time spent chasing elusive software issues. This webinar includes a live demo and Q&A.

I have the OA for the NVIDIA hardware internship at my college on October 22; can someone suggest the types of technical and aptitude questions asked, and as a BTech fresher, what kind of projects are sufficient?

I've been looking for internships for a while, mostly all of them require that you either study in or have the citizenship of the country in which the opportunity exists (mostly in US, Canada, and EU).

What can I do as a foreign student who wants to get a chance in such a field, especially that neither my uni or country overall offers a lot of opportunities for us?

any clue on this, when i flash the r5 using remote proc the r5 core shows to the xsdb as :

debug logic reset

if not flashing from remoteproc, i can stop and have access at the r5 but the problem is that i cannot flash it bcs tcm banks are powered off ( i am using linux on the a53)

I am attaching also the picture

I've made it to the technical interview for HFT Hardware Engineer Intern role and was wondering if anyone has any advice on what to prepare for?

Also, if anyone who's been through a similar AC would be willing to do a mock interview with me, I'd really appreciate it. Thanks!

I have been working with FPGAs for just about 10 years now. And I just realized that I have never done a CDC FIFO. Well... Maybe back in uni as some paper exercise.

It's such a weird gap too. Since it's like the first answer anyone gives whenever you want to transfer a lot of data across clock domains. But I just haven't needed a hardware FIFO for that yet.

So I spent the afternoon implementing one from scratch and shoving every edge case I could think of at it. Just as a learning exercise.

Have you found any weird gaps in your own knowledge?

renulev/sap-1: Malvino's SAP-1 implemented in Verilog

I used Icarus verilog for this project. GTKWave output looks clean.
I also used Makefile for automation.

I'm a third-year EEE student at UCL and I'm struggling to get past the initial application stage for FPGA internships. I rarely seem to receive online assessments and keep getting rejected after submitting my applications.

I'm particularly interested in FPGA engineering roles at trading firms, but I'm not sure whether the issue is my CV, lack of relevant experience, or something else.

For anyone who's been through this process, especially EEE students or people applying for FPGA/HFT internships, what helped you get more OAs? Is there anything specific recruiters look for at the CV screening stage?

Any advice would be really appreciated!

Hii guys,

I'm currently a student studying computer engineering and I was looking around for careers I could do with my degree.

I found out abt FPGA's later on and I really want to get into it.

The issue is that the engineering department in my school just started (I'm in the first set ever) so there's basically zero hardware-anything at all. I feel like it's so bad cause they've not even bothered to try to teach us any code in the last 3 years at this school.

Regardless I took it upon myself to learn something that will help me even a little when I finish from here and go do my masters, so I started with embedded and got an Arduino kit to start trying to learn with AI. I'm probably still very far off cause learning with AI isn't exactly ideal especially if it's a free version.

Joining this community has really opened my eyes to see how much farther the gap is and it feels like I'm in a hole trying to crawl out just to get to the base line

Any thoughts and advice would be very helpful

Thank you very much 🙏🏾🙏🏾

What sort of questions may I expect for

SoC Platform Engineer, FPGA interview ?

I'm curious how people doing FPGA work professionally actually spend their time, especially the parts of the workflow that are still frustrating.

Not looking for a generic "Vivado sucks" answer (although that's fair 😅). I'm more interested in specific examples.

A few things I'd love to hear about:

• What part of your workflow consistently takes more time than you think it should?
• What tasks do you find yourself doing manually or repeatedly?
• What tools do you use day-to-day besides Vivado/Quartus/etc.? Editors, scripts, simulation, verification, CI, version control, internal tools, etc.
• Are there any tools you've built internally because existing ones weren't good enough?
• How do you handle Git/version control for RTL, constraints, IP, block designs, generated files, and tool projects?
• What does debugging usually look like when something doesn't work?
• Which parts of verification are the most painful?
• How painful is moving between RTL changes → simulation → synthesis → implementation → hardware debugging?
• Are there parts of working with constraints/timing that you wish had better tooling?
• Do you use AI tools like Claude, ChatGPT, Copilot, Cursor, Claude Code, etc. for FPGA work? If so, what are they actually useful for?
• Where have AI tools been useless or actively dangerous? Where have they been good?
• If you could magically fix one part of the FPGA development workflow, what would you fix?

I'm especially interested in answers from people working on production FPGA designs, but hobbyist/academic perspectives are welcome too.

Would also love to know roughly what kind of FPGA work you do (industry/domain, team size, Xilinx/Altera/Lattice/etc.) since I imagine the pain points vary quite a bit.

Without any context, if my interview went like an 8 on 10, what chances do i have to move forward for a position (intern)

The position is in hardware background so less saturated then swe ig

Hello,

I'm working on a Zynq UltraScale+ RFSoC design the RFDC ADC stream (128-bit TDATA, 8 × int16 per beat, 309.5 MHz clk_adc0) goes through an AXI4-Stream Clock Converter into an AXI DMA. The DMA side runs on a separate clock domain from a clk_wiz output.

I put ILAs on both sides of the converter to check data integrity on a 128-beat (1024-sample) burst delimited by TVALID/TLAST. At that time the output side ran at 100 MHz, i.e. about 3× slower than the input.

What I have saw

Input side: 128 contiguous valid beats in 0.41 µs, with tready never deasserted during the burst.

Output side: the same 128 beats come out contiguously at 100 MHz (1.28 µs), and TLAST is on the last beat.

A sine fit on both captures gives the same frequency, amplitude and residual, so no beat or samples seems lost or duplicated.

So the converter's FIFO must have absorbed the burst, with a peak occupancy of roughly 87 beats, which means a depth of at least that. Now I'd like to know exactly how deep it is.

Does anyone know the actual FIFO depth of axis_clock_converter? Is it a fixed value, or does it depend on parameters such as the clock ratio, the synchronization stages or the data width?

Is the depth user-configurable (a CONFIG. property, a hidden GUI option, an HDL parameter)?

I'm asking because I want to know the maximum size length I can capture without losing samples

Thanks :)

Hi everyone!

If anyone have appeared for the IMC Trading written test, could you please share the questions you remember? I’d be really grateful!

Also, if you cleared the test, could you share what to expect in the interview round and what topics I should focus on preparing?

Thanks in advance! 😊

I made a working correlator receiver in VHDL for my basys3 that can read from a raw IQ .bin file captured by an RTL-SDR and decode and display airplane positions and information. I want to make it work in real time and not just simulations but im having trouble figuring out how i can get the RTL-SDR stream to the basys3 without doing all of the signal detection on a pc first.

From what i understand the basys3 uart maxes out at 1 Mbps but adsb raw IQ sampling needs at least 32 Mbps. This is my second project on the basys3 and i dont have any other hardware but im open to any (cheap) suggestions that make this as little pc dependent as possible.

Quiero ver los proyectos de algunos usuarios para saber cuál experimentar primero, soy muy principiante pero me gustaría que se puede hacer más con las FPGA que no he encontrado en Youtube

Hi!

I'm the developer of SILICON, a free and open-source digital circuit simulator written in C++ using Qt6.

It's going to become my Bachelor Thesis (I'm studying Computer Engineering @ Genoa Italy) and we are exeperimenting with It in the digital design course at my university (UniGe).

SILICON aims to provide a modern environment for designing and simulating digital circuits, primarily for educational purposes (like LogiSim), while gradually incorporating more advanced EDA capabilities.

Some of its current features include:

• Graphical circuit editor with logic gates, arithmetic components, flip-flops, registers, ROMs, and more.

• Event-driven digital simulation with multi-bit buses and four-state logic.

• Live waveform visualization and input waveform editing with FST firstclass support.

• Verilog import/export through Yosys integration.

• Automatic circuit placement.

• Reusable subcircuits and multi-document projects.

• Integrated code and binary editors, along with experimental ISA tooling.

• WASM web build

I'd especially appreciate feedback about the user interface, simulation behavior, missing features, and any bugs you encounter.

If you want to contribute as a dev send me a DM. I especially need help with MacOS support and Windows packaging.